NVIDIA design jobs
NVIDIA has 184 open design roles as of our latest check. Get an email when a new one is posted — without refreshing their careers page.
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Design hiring at NVIDIA
Data updated 11 hours agoOpen roles
184
in design
New · 7 days
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building history
Locations
13
ATS
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Open design roles at NVIDIA
- Senior Mixed Signal Circuit Design EngineerUS, CA, Santa Clara · first seen
- ASIC Design Engineer - Performance MonitoringIndia, Bengaluru · first seen
- Senior DTCO Engineer, CPU Physical Design4 Locations · first seen
- Hardware Design Validation Engineer - Memory Subsystem - New College Grad 2026US, CA, Santa Clara · first seen
- Senior Circuit Design EngineerUS, CA, Santa Clara · first seen
- VLSI Design Automation Software Engineer2 Locations · first seen
- Senior Mask Layout Design Engineer2 Locations · first seen
- PCIe Design Verification Intern - Summer 2027US, TX, Austin · first seen
- Senior Board Design EngineerIsrael, Yokneam · first seen
- Signal Integrity and PCB Design EngineerUS, CA, Santa Clara · first seen
- Senior IP Design Verification Engineer - XBAR IPIndia, Bengaluru · first seen
- Senior Mask Layout Design Engineer2 Locations · first seen
- Senior Physical Design Engineer2 Locations · first seen
- ASIC Physical Design EngineerChina, Shanghai · first seen
- PCIe Design Verification Intern - Spring 2027US, CA, Santa Clara · first seen
- Senior Circuit DesignerUS, CA, Santa Clara · first seen
- Senior ASIC Design Engineer2 Locations · first seen
- Senior ASIC Design Engineer - XBAR IPIndia, Bengaluru · first seen
- Manager, Silicon Circuit Co-Design — Silicon Co-Design GroupChina, Shanghai · first seen
- Senior Analog Layout Design EngineerIsrael, Yokneam · first seen
- PhD Research Intern, Electronic Design Automation - 2027US, CA, Santa Clara · first seen
- 8. Mixed Signal Design Engineer (MSD10), Sr. Mixed Signal Design Engineer (SMSD10) & Principal Mixed Signal Design Engineer (PMSD10)US, CA, Santa Clara · first seen
- Senior Board Design Hardware Engineer2 Locations · first seen
- Manager, Chip DesignIsrael, Tel Aviv · first seen
- Mixed Signal Design Engineer - New College Grad 20262 Locations · first seen
- ASIC Design Engineer - New College Grad 2027US, CA, Santa Clara · first seen
- Hardware Manager, Switch DesignIsrael, Raanana · first seen
- Senior ASIC Design Verification Engineer - LPU6 Locations · first seen
- Senior SRAM Engineer, Circuit DesignUS, CA, Santa Clara · first seen
- Senior Manager, Silicon Speed Productization — Silicon Co-Design GroupUS, CA, Santa Clara · first seen
- Senior ASIC Design Engineer, GPU Core Pipeline IPIndia, Bengaluru · first seen
- PhD Research Intern, AI Accelerator Design and VLSI - 2027US, CA, Santa Clara · first seen
- Senior Design Verification Engineer - HardwareChina, Shanghai · first seen
- ASIC Design Engineer, Tools and Methodology DevelopmentUS, TX, Austin · first seen
- Physical Design Intern, VLSI - 20272 Locations · first seen
- ASIC Design Engineer – Clocks IP2 Locations · first seen
- Physical Design Engineer (RDSS Intern)Taiwan, Hsinchu · first seen
- Senior Technical Program Manager – Silicon Co-DesignUS, CA, Santa Clara · first seen
- Senior Software Engineer, Chip Design2 Locations · first seen
- Senior Silicon Circuit Co-Design EngineerUS, CA, Santa Clara · first seen
- VLSI Physical Design CAD Intern - Summer 2027Taiwan, Hsinchu · first seen
- Senior Chip Design EngineerIsrael, Beer Sheva · first seen
- PCB Design Layout Engineer2 Locations · first seen
- Manager, Project Management - Chip DesignIsrael, Tel Aviv · first seen
- Silicon Co-design Intern - 2027China, Shanghai · first seen
- PCB Design Layout EngineerUS, CA, Santa Clara · first seen
- Senior System Design EngineerUS, CA, Santa Clara · first seen
- ASIC Design and Verification Intern, SOC - 2027China, Shanghai · first seen
- Director, Global Workplace DesignUS, CA, Santa Clara · first seen
- SOC Design Team Methodology Intern - 2027China, Shanghai · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- Senior Mask Layout Design Engineer2 Locations · first seen
- Senior System Design Test ArchitectIsrael, Yokneam · first seen
- Senior Thermal Design EngineerUS, CA, Santa Clara · first seen
- Senior Mask Layout Design Engineer2 Locations · first seen
- Senior Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- ASIC Floorplan Design Engineer - New College Grad 2026US, CA, Santa Clara · first seen
- Physical Design, VLSI - New College Grad 20272 Locations · first seen
- Design Verification Engineer (RDSS Intern)Taiwan, Hsinchu · first seen
- Senior Physical Design Backend EngineerIsrael, Tel Aviv · first seen
- Mechanical Design Team ManagerIsrael, Yokneam · first seen
- ASIC Physical Design Intern - 2027China, Shanghai · first seen
- ASIC Engineering Intern, Networking Chip Design - 2027China, Shanghai · first seen
- ASIC Physical Design Intern - 2027Taiwan, Hsinchu · first seen
- ASIC Physical Design Engineer (RDSS Intern)Taiwan, Hsinchu · first seen
- Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- Physical Design Power Optimization and Modeling Engineer2 Locations · first seen
- Senior ASIC Power Management Micro Architect, Chip Design2 Locations · first seen
- Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- NVIDIA 2027 Internships: Hardware Design for Test (DFT)US, CA, Santa Clara · first seen
- NVIDIA 2027 Internships: Hardware Physical Design / VLSIUS, CA, Santa Clara · first seen
- NVIDIA 2027 Internships: Digital Circuit DesignUS, CA, Santa Clara · first seen
- NVIDIA 2027 Internships: Mixed Signal DesignUS, CA, Santa Clara · first seen
- CPU Design Methodology Engineer4 Locations · first seen
- NVIDIA 2027 Internships: Hardware ASIC DesignUS, CA, Santa Clara · first seen
- Senior Mask Design Engineer – HardwareTaiwan, Hsinchu · first seen
- Physical Design STA CAD Engineer2 Locations · first seen
- Principal Photonics IC Design EngineerUS, CA, Santa Clara · first seen
- Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU5 Locations · first seen
- Circuit Design Engineer - HardwareChina, Shanghai · first seen
- Physical Design STA Engineer2 Locations · first seen
- Interposer Design EngineerIsrael, Yokneam · first seen
- Enterprise AV Design and Collaboration EngineerUS, CA, Santa Clara · first seen
- Principal Engineer, Project Management - Chip DesignIsrael, Tel Aviv · first seen
- PCB Design Layout EngineerUS, CA, Santa Clara · first seen
- Senior Mask Design Engineer – HardwareIndia, Bengaluru · first seen
- Senior ASIC Physical Design Engineer, Cache Coherent Interconnects2 Locations · first seen
- Senior ASIC Design Engineer2 Locations · first seen
- Senior Design Integration EngineerIsrael, Tel Aviv · first seen
- Senior Mask Design Engineer - Hardware2 Locations · first seen
- ASIC Physical Design and Timing Engineer - New College Grad 2026US, CA, Santa Clara · first seen
- Senior Circuit Design EngineerIndia, Bengaluru · first seen
- System Design Intern, LDE - 2027Taiwan, Taipei · first seen
- HSIO Validation Lead – Silicon Co-DesignUS, CA, Santa Clara · first seen
- Package Design Methodology Engineer3 Locations · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- Senior Software R&D Engineer, VLSI Physical Design2 Locations · first seen
- Chip Design EngineerIsrael, Tel Aviv · first seen
- Senior ASIC Design Engineer - GPU3 Locations · first seen
- Senior EDA Engineer, SOC Design MethodologyUS, CA, Santa Clara · first seen
- ASIC Design and STA Engineer2 Locations · first seen
- Senior Speed Characterization Engineer - Silicon Co-Design GroupUS, CA, Santa Clara · first seen
- Applied Research Engineer, Chip DesignUS, CA, Santa Clara · first seen
- Senior Mixed Signal and Analog Circuit Designer2 Locations · first seen
- Senior Design Verification Engineer - HardwareChina, Shanghai · first seen
- Board Design Engineer, SustainIsrael, Yokneam · first seen
- Senior Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- Senior Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- Principal Chip Lead, Silicon Co-Design GroupUS, CA, Santa Clara · first seen
- Physical Design Engineer2 Locations · first seen
- Senior Hardware System Design EngineerUS, OR, Hillsboro · first seen
- Senior Board Design Engineer, Electro OpticalIsrael, Yokneam · first seen
- Applied Agentic AI Lead, Partner Co-Design2 Locations · first seen
- CAD Developer, IR, Timing and Physical Design OptimizationChina, Shanghai · first seen
- Senior Chip Design and Verification EngineerIsrael, Tel Aviv · first seen
- Senior Infrastructure Automation Engineer - Silicon Co-Design GroupChina, Shanghai · first seen
- Physical Design EngineerIsrael, Tel Aviv · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- Senior SOC Clocks RTL Design Engineer2 Locations · first seen
- Senior Mixed Signal Design EngineerUS, CA, Santa Clara · first seen
- Senior ASIC Physical Design Engineer, Netlisting2 Locations · first seen
- Senior Mask Design Engineer – Hardware6 Locations · first seen
- ASIC TOP Floorplan Design EngineerChina, Shanghai · first seen
- Senior ASIC Design Engineer – Clocks IP2 Locations · first seen
- System Design Engineer - LDE (RDSS Intern)Taiwan, Taipei · first seen
- Senior IP Design Verification Engineer - XBAR IPIndia, Bengaluru · first seen
- Senior ASIC Verification Engineer - Networking Chip DesignChina, Shanghai · first seen
- Physical Design Engineer, Synthesis and ImplementationUS, MA, Westford · first seen
- Physical Design Backend Engineer2 Locations · first seen
- Senior Physical Design Interposer Engineer3 Locations · first seen
- SOC Clocks RTL Design Engineer3 Locations · first seen
- Senior Mixed Signal Design Engineer2 Locations · first seen
- Senior SoC Design EngineerIndia, Bengaluru · first seen
- Senior ASIC Design Engineer - DFTUS, CA, Santa Clara · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- ASIC Design Engineer, ClocksChina, Shanghai · first seen
- System Verification Co-Design Engineer - Speed and RelUS, CA, Santa Clara · first seen
- Senior Software Engineer - SONiC Design GroupIsrael, Raanana · first seen
- PCB Design Layout EngineerUS, CA, Santa Clara · first seen
- Hardware Board Design EngineerIsrael, Yokneam · first seen
- Senior Physical Design and Timing Engineer4 Locations · first seen
- Senior Power Integrity Co-Design EngineerUS, CA, Santa Clara · first seen
- Senior ASIC Design Engineer - XBAR IPIndia, Bengaluru · first seen
- System Design Engineer - New College Grad 2026US, CA, Santa Clara · first seen
- Senior Mechanical Product Design EngineerUS, CA, Santa Clara · first seen
- Senior SOC Design Engineer - Networking GroupIndia, Bengaluru · first seen
- Senior Circuit Design Engineer - Power Modeling and Simulation2 Locations · first seen
- ASIC Design Engineer - HardwareUS, TX, Austin · first seen
- Senior Thermal Solutions Design EngineerUS, CA, Santa Clara · first seen
- Senior Physical Design Engineer2 Locations · first seen
- ASIC Design EngineerUS, CA, Santa Clara · first seen
- Mixed Signal Design Validation EngineerUS, CA, Santa Clara · first seen
- Board Design Engineer, NVLINK2 Locations · first seen
- Photonic Mixed Signal Design Validation EngineerUS, CA, Santa Clara · first seen
- Chip Design EngineerIsrael, Tel Aviv · first seen
- Senior ASIC Design EngineerUS, CA, Santa Clara · first seen
- Senior Circuit Design EngineerUS, CA, Santa Clara · first seen
- Senior Chip Design Verification Engineer2 Locations · first seen
- System Design EngineerUS, CA, Santa Clara · first seen
- Senior Design Verification Engineer - GPU Memory SubsystemUS, NC, Durham · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- Logic Design Engineer, CPU CoreIsrael, Yokneam · first seen
- Senior Board Design EngineerUS, CA, Santa Clara · first seen
- Senior Physical Design EngineerUS, CA, Santa Clara · first seen
- ASIC Physical Design Engineer, Netlisting - New College Grad 20262 Locations · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- Senior Photonic Layout Design EngineerUS, CA, Santa Clara · first seen
- Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- Senior Physical Design and Timing EngineerUS, MA, Westford · first seen
- Senior Design Engineer, Coherent High Speed InterconnectUS, CA, Santa Clara · first seen
- Senior Physical Design Methodology Engineer, Innovus Flows4 Locations · first seen
- Senior Physical Design EngineerUS, MA, Westford · first seen
- Senior Physical Design Engineer2 Locations · first seen
- Software Design Engineer - SONiC GroupIsrael, Raanana · first seen
- Principal CPU Architect - High-Performance and Physical Design3 Locations · first seen
- Senior Circuit Design Engineer - Noise2 Locations · first seen
- Circuit Design Engineer - Standard CellUS, CA, Santa Clara · first seen
- Senior IP Design Verification Engineer - XBAR IPIndia, Bengaluru · first seen
- Senior Manager, System Co-Design Manager - SCG TeamUS, CA, Santa Clara · first seen
- Senior SOC Design EngineerUS, CA, Santa Clara · first seen
- Software R&D Engineer, VLSI Physical Design - New College Grad 20262 Locations · first seen
- Director, ADAS User Experience Product - Autonomous VehiclesUS, CA, Santa Clara · first seen
- Senior Manager, System Integration – Silicon Co-Design GroupUS, CA, Santa Clara · first seen
Links go straight to NVIDIA’s own posting.
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