NVIDIA design jobs — get alerted first
NVIDIA has 99 open design roles right now. Get an email the moment a new one is posted — without refreshing their careers page.
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Design hiring at NVIDIA
Data updated 3 hours agoOpen roles
99
in design
New · 7 days
99
first seen this week
Locations
15
2 remote
ATS
Workday
Open design roles at NVIDIA
- Circuit Design Engineer - New College Grad 2026US, CA, Santa Clara · first seen
- Chip Design Manager2 Locations · first seen
- Senior DFT Design Engineer2 Locations · first seen
- Senior Thermal Solutions Design EngineerUS, CA, Santa Clara · first seen
- Physical Design Engineer3 Locations · first seen
- ASIC Design EngineerIndia, Bengaluru · first seen
- Senior ASIC Design Engineer - NOC IPIndia, Bengaluru · first seen
- Senior Digital Design Verification Engineer - HardwareUS, CA, Santa Clara · first seen
- Senior Physical Design Engineer2 Locations · first seen
- Senior Mixed Signal Circuit Design Engineer2 Locations · first seen
- ASIC Hardware Design Engineer - New College Grad 2026US, TX, Austin · first seen
- Senior IP Design Verification Engineer - XBAR IPIndia, Bengaluru · first seen
- System Design EngineerTaiwan, Taipei · first seen
- Senior ASIC Design Verification Engineer - LPU2 Locations · first seen
- Senior Mixed Signal Design EngineerUS, CA, Santa Clara · first seen
- Board Design Engineer, NVLINK2 Locations · first seen
- Senior SRAM Circuit Design EngineerUS, CA, Santa Clara · first seen
- Physical Design Engineer2 Locations · first seen
- Chip Design EngineerIsrael, Tel Aviv · first seen
- AI Chip Design Engineer - New College Grad 2026US, CA, Santa Clara · first seen
- Photonic Mixed Signal Design Validation EngineerUS, CA, Santa Clara · first seen
- Physical Design Power Integrity EngineerIsrael, Yokneam · first seen
- Senior Logic Design Engineer, CPU CoreIsrael, Yokneam · first seen
- Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- Senior Chip Design Verification Engineer2 Locations · first seen
- Physical Design Backend STA Engineer2 Locations · first seen
- Senior AI Chip Design Engineer2 Locations · first seen
- Senior Physical Design Engineer2 Locations · first seen
- Senior Chip Design Verification Engineer2 Locations · first seen
- Senior Embedded Graphic Software EngineerTaiwan, Taipei · first seen
- Senior Chip Design Engineer2 Locations · first seen
- Lead Design Engineer - Autonomous VehiclesUS, CA, Santa Clara · first seen
- Principal Verification Chip Design Engineer2 Locations · first seen
- Senior ASIC Design Engineer - LPUCanada, Remote · first seen
- Senior ASIC Design Engineer - LPU6 Locations · first seen
- ASIC Design EngineerUS, CA, Santa Clara · first seen
- Senior ASIC Verification Engineer - Networking Chip DesignChina, Shanghai · first seen
- Senior Mask Design Engineer - Hardware2 Locations · first seen
- Senior Mask Design Engineer - Hardware2 Locations · first seen
- ASIC Design Engineer, BOOT, Functional Safety and Power Management2 Locations · first seen
- Senior ASIC Design Engineer, High Speed IO2 Locations · first seen
- Senior Mixed Signal Design EngineerUS, CA, Santa Clara · first seen
- Senior Mask Design Engineer - HardwareUS, CA, Santa Clara · first seen
- Senior Chip Design Verification Engineer2 Locations · first seen
- Senior Mask Design Engineer - Hardware2 Locations · first seen
- System Design Power Validation EngineerTaiwan, Taipei · first seen
- Mixed Signal Design Validation EngineerUS, CA, Santa Clara · first seen
- Senior Board Design Hardware Engineer2 Locations · first seen
- Senior Circuit Design EngineerUS, CA, Santa Clara · first seen
- Physical Design EngineerTaiwan, Hsinchu · first seen
- Senior Mixed Signal Design EngineerUS, CA, Santa Clara · first seen
- Senior Board Design Hardware Engineer2 Locations · first seen
- Senior ASIC Design EngineerUS, CA, Santa Clara · first seen
- Senior Mask Design Engineer - HardwareUS, CA, Santa Clara · first seen
- Senior Board Design Engineer, SustainIsrael, Yokneam · first seen
- Senior CPU Design Engineer6 Locations · first seen
- Senior Mixed-Signal Design EngineerUS, CA, Santa Clara · first seen
- Senior ASIC Design EngineerUS, CA, Santa Clara · first seen
- Senior Mixed Signal Design Verification Engineer2 Locations · first seen
- Digital Circuit Design Engineer2 Locations · first seen
- Mixed Signal Design Validation EngineerUS, CA, Santa Clara · first seen
- Senior Logic Design Engineer, Cache Coherent Interconnects2 Locations · first seen
- Senior Chip Design Verification Engineer2 Locations · first seen
- SAI Software Design Engineer2 Locations · first seen
- Senior Digital Design Verification Engineer - Hardware2 Locations · first seen
- ASIC Design Engineer - CircuitsIndia, Bengaluru · first seen
- Senior Chip Design EngineerIsrael, Tel Aviv · first seen
- Senior Director, Global Workplace Strategy, Planning and DesignUS, CA, Santa Clara · first seen
- Senior Mask Design Engineer - HardwareUS, CA, Santa Clara · first seen
- Senior Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- VLSI Design Automation Software EngineerUS, MA, Westford · first seen
- Logic Design Engineer, CPU CoreIsrael, Yokneam · first seen
- Physical Design Backend EngineerIsrael, Tel Aviv · first seen
- Senior Physical Design Engineer3 Locations · first seen
- Senior ASIC Design Verification Engineer - LPUCanada, Remote · first seen
- Senior Mixed Signal Design EngineerUS, CA, Santa Clara · first seen
- Senior Mask Design Engineer - HardwareUS, CA, Santa Clara · first seen
- Senior Mixed Signal Design EngineerUS, CA, Santa Clara · first seen
- Senior Platform Design EngineerUS, CA, Santa Clara · first seen
- Memory Mask Design EngineerIndia, Bengaluru · first seen
- Senior Industrial DesignerUS, CA, Santa Clara · first seen
- Senior Mixed Signal Design Engineer2 Locations · first seen
- ASIC Physical Design EngineerChina, Shanghai · first seen
- Senior C++ Software Engineer - Chip Design Tools4 Locations · first seen
- Manager, System Design Tools and MethodologyUS, CA, Santa Clara · first seen
- ASIC Physical Design Engineer, Netlisting - New College Grad 20262 Locations · first seen
- Senior Chip Design Verification EngineerIsrael, Tel Aviv · first seen
- Senior Physical Design Engineer2 Locations · first seen
- ASIC Design and STA Engineer2 Locations · first seen
- Senior ASIC Design EngineerUS, CA, Santa Clara · first seen
- Senior Chip Design Engineer, Formal VerificationIsrael, Tel Aviv · first seen
- Electrical Design Engineer, AI Factory Deployment6 Locations · first seen
- Senior Logic Design EngineerUS, CA, Santa Clara · first seen
- Senior Physical Design EngineerUS, CA, Santa Clara · first seen
- Senior Physical Design Engineer2 Locations · first seen
- Senior Board Design Hardware Engineer2 Locations · first seen
- Senior Design Verification Engineer - GPU Memory SubsystemUS, NC, Durham · first seen
- Principal Thermal Mechanical Photonic DesignerUS, CA, Santa Clara · first seen
- Senior Circuit Design Engineer - PowerUS, CA, Santa Clara · first seen
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